1. Field of the Invention
The present invention relates to an output circuit for integrated circuit devices, such as CMOS (complementary MOS) LSIs, and more particularly to an output circuit of this kind, which includes a plurality of CMOS inverters which drive a plurality of respective loads which are substantially capacitive (hereinafter referred to as "capacitive load(s)") connected to the output circuit in response to a multi-bit data signal.
2. Prior Art
Conventionally, an output circuit for CMOS LSIs shown in FIG. 1 is known. An IC chip 10 has formed thereon a circuit, not shown, for generating data signals IN1 to INn indicative of n-bit data (n being an integer of 3 or more), and an output circuit for transferring the data signals IN1 to INn from the above-mentioned circuit to output terminals O1 to On. The output circuit includes tristate output blocks provided for respective different-bit data signals IN1 to INn, each having a prebuffer as designated by PB1 and an output buffer as designated by PB1.
In the output block which handles the data signal IN1, the prebuffer PB1 is comprised of an inverter IV which receives an output enable signal OEN, a NAND gate NAa which receives an output signal OE from the inverter IV and the data signal IN1, and a NAND gate NAb which receives the output enable signal OEN and the data signal IN1. The output buffer OB1 is formed by a CMOS inverter comprised of a P-channel MOS transistor P1 and an N-channel MOS transistor N1 which have their drains connected together. The transistor P1 has its source connected via a power wiring V.sub.D to a power terminal T1 which is supplied with a high voltage or potential V.sub.DD, and the transistor N1 has its source connected via a power wiring V.sub.S to a power terminal T2 which is supplied with a low voltage or potential V.sub.SS. The transistors P1 and N1 have their gates supplied, respectively, with an output signal from the NAND gate NAa and an output signal from the NAND gate NAb to be driven thereby.
When the output enable signal OEN is at a low ("L") level, the output signal OE from the inverter IV assumes a high ("H") level. Accordingly, the NAND gates NAa and NAb both generate output signals which are inverted in phase to the data signal IN1. For example, when the data signal IN1 goes high ("H"), the output signals from the gates NAa, NAb both go low ("L"), so that the transistors P1, N1 are turned on and off, respectively, and hence an output signal from the output terminal O1 goes "H". When the data signal IN1 goes "L", the gate output signals change inversely to the above to turn the transistors into inverse states to the above so that the output signal from the output terminal O1 goes "L".
On the other hand, when the output enable signal OEN goes "H", the output signal OE from the inverter IV goes "L", so that the NAND gates NAa and NAb generate output signals at "H" and "L", respectively, irrespective of the level of the data signal IN1, and hence the transistors P1 and N1 are both turned off to bring the output terminal O1 into a high-impedance (or floating) state.
The output blocks which handle the data signals IN2 to INn are identical in construction and operation with the output block handling the data signal IN1, described above. In the figure, reference numerals PB2 to PBn designate prebuffers similar to the prebuffer PB1, OB2 to OBn output buffers similar to the output buffer OB1, P2 to Pn P-channel MOS transistors similar to the transistor P1, and N2 to Nn N-channel MOS transistors similar to the transistor N1. Capacitive loads are connected to the output terminal O1 and output terminals O2 to On, respectively.
The IC chip 10 is packed in an IC package, not shown. The IC package has leads connected to inputs of other LSI(s) or the like via a connector or a common bus. The power terminals T1, T2 and the output terminals O1 to On correspond to leads of the IC package. Inductances L.sub.D and LS exist between the leads corresponding to the power terminals T1, T2 and the IC chip 10, which are ascribed to IC package leads, bonding wires, etc. The inductances L.sub.D, LS are usually of the order of several nH to about 2 dozens nH. The capacitive loads C1 to Cn connected to the output terminals O1 to On are equivalent to substantial input capacitance present at the inputs of an LSI(s) connected to the output of the output device and wiring capacitance, and desirably they should not exist.
The output circuit according to the prior art constructed as above has the disadvantage that a malfunction can be caused by discharge of a capacitive load(s) such as C1 when a transistor forming the output buffer, such as N1, is turned on.
FIG. 2 shows essential parts of the output circuit of FIG. 1 for use in explaining the above disadvantage. In the figure, elements corresponding to those in FIG. 1 are designated by identical reference numerals.
In FIG. 2, reference numeral OB2 designates the output buffer handling the data signal IN2, which is formed by a CMOS inverter comprised of a P-channel MOS transistor P2 and an N-channel MOS transistor N2 which have their drains connected together.
The transistors P2, N2 are disposed to be turned off and on, respectively, when "H" level signals are applied to the gates thereof, whereby the output terminal O2 generates a "L" level output signal. In this state, if the input signals to the gates of the transistors P1, N1 of the output buffer OB1 rise from "L" level to "H" level, the transistors P1, N1 turn off and on, respectively, whereby the electric charge of the capacitive load C1 is discharged through a path of output terminal O1, transistor N1, power wiring V.sub.S, and inductance L.sub.S, so that discharge current I flows through the path.
When the discharge current I flows in the inductance L.sub.S, an electromotive force .DELTA.V is generated in the inductance L.sub.S, which is expressed by the following equation (1): EQU .DELTA.V=-L.sub.S .times.dI/dt (1)
Consequently, a bound of voltage occurs due to the electromotive force .DELTA.V at a point X corresponding to the source of the transistor N2. A waveform (ringing waveform) similar to the waveform of voltage bound at the point X also appears at the output terminal O2, though the potential change at the output terminal O2 is somewhat dull due to a time constant determined by the On-state resistance of the transistor N2 and the capacitance of the capacitive load B2.
FIG. 3 shows the ringing waveform WO2 appearing at the output terminal O2 as well as the voltage waveform WO1 appearing at the output terminal O1. If the LSI connected to the output of the output circuit is a TTL (transistor-transistor logic) type, the "L" input voltage VIL to the TTL (the upper limit voltage that can be recognized to a "L" input voltage by the LSI) is 0.8 V. Therefore, if a peak of the ringing waveform WO2 exceeds the value VIL (=0.8 V), the LSI can erroneously recognize the ringing waveform WO2 as a "H" level signal and hence malfunction, though the output signal at the output terminal O2 is at "L" level.
Further, when the gate voltages applied to the transistors P2, N2 are at "L" level (the output signal at the output terminal O2 is at "H" level), if the gate voltages to the transistors P1, N1 change from "H" level to "L" level, the transistors P1, N1 turn on and off, respectively, whereby the capacitive load C1 is charged by current flowing through a path of inductance L.sub.D, power wiring V.sub.D, transistor P1, and output terminal O1. The charge current flowing on this occasion causes a ringing waveform as indicated by Q16 in FIG. 7 to occur at a point Y corresponding to the source of the transistor P1. This ringing waveform is transmitted to the capacitive load C2 via the transistor P2 and the output terminal O2. Consequently, the LSI connected to the output can erroneously recognize the ringing waveform as a "L" level signal and hence malfunction, though the output signal at the output terminal O2 is at "H" level.
One measure to prevent a malfunction of a device connected to the output due to charging or discharging of the capacitive load is to provide as the power wiring V.sub.S a plurality of separate power wirings, respectively, for the transistors N1, N2, . . . Nn and provide as the power wiring V.sub.D a plurality of separate power wirings, respectively, for the transistors P1, P2, . . . Pn. However, according to this measure, if the number of bits of the data signals employed is large, the number of power wirings used becomes very large, i.e. as many as 2.times.n (e.g. 16 if n=8).